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1 of 30 may 4, 2004 ? 2004 integrated device technology, inc. dsc 6402 idt and the idt logo are registered trademar ks of integrated device technology, inc. idt tm interprise tm integrated communications processor 3.3v and 2.5v devices device overview the rc32333 device is a member of the idt? interprise? family of integrated communications processo rs. this product incorporates a high-performance, low-cost 32-bit cpu core with functionality common to a large number of embedded applications. the rc32333 integrates these functions to enable the use of low-cost pc commodity market memory and i/o devices, allowing the aggressive price/performance characteristics of the cpu to be real ized quickly into low-cost systems. the rc32333 device is available with either a 3.3v or 2.5v operating voltage. differences between the two versions are noted where appli- cable. features rc32300 32-bit microprocessor ? up to 150 mhz operation ? enhanced mips-ii instruction set architecture (isa) ? cache prefetch instruction ? conditional move instruction ? dsp instructions ? supports big or little endian operation ? mmu with 32 page tlb ? 8kb instruction cache, 2-way set associative ? 2kb data cache, 2-way set associative ? cache locking per line ? programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management ? compatible with a wide variety of operating systems local bus interface ? up to 75 mhz operation ? 23-bit address bus ? 32-bit data bus ? direct control of local memory and peripherals ? programmable system watch-dog timers ? big or little endian support interrupt controller simp lifies exception management four general purpose 32-bit timer/counters programmable i/o (pio) ? input/output/interrupt source ? individually programmable sdram controller (32-bit memory only) ? 4 banks, non-interleaved ? up to 512mb total sdram memory supported ? implements full, direct control of discrete, sodimm, or dimm memories ? supports 16mb through 512mb sdram device depths ? automatic refresh generation block diagram figure 1 rc32333 block diagram local memory/io control interrupt contro l dma control uart 32-bit timers spi control programmable i/o pci bridge idt peripheral bus riscore 32300 enhanced mips-ii isa integer cpu rc5000 compatible cp0 32-page tlb ejtag in-circuit emulator interface 2kb 2-set, lockable data cache 8kb 2-set lockable instr. cache ipbus bridge sdram control 79rc32333
2 of 30 may 4, 2004 idt 79rc32333 serial peripheral interface (spi) master mode interface uart interface ? 16550 compatible uart ? baud rate support up to 1.5 mb/s memory & peripheral controller ? 6 banks, up to 8mb per bank ? supports 8-,16-, and 32-bit interfaces ? supports flash rom, sram, dual-port memory, and peripheral devices ? supports external wait-state generation ? 8-bit boot prom support ? flexible i/o timing protocols 4 dma channels ? 4 general purpose dma, each with endianess swappers and byte lane data alignment ? supports scatter/gather, chaining via linked lists of records ? supports memory-to-memory, memory-to-i/o, memory-to- pci, pci-to-pci, and i/o-to-i/o transfers ? supports unaligned transfers ? supports burst transfers ? programmable dma bus tr ansactions burst size (up to 16 bytes) pci bus interface ? 32-bit pci, up to 50 mhz ? revision 2.2 compatible ? target or master ? host or satellite ? three slot pci arbiter ? serial eeprom support, for loadi ng configuration registers off-the-shelf d evelopment tools jtag interface (ieee std. 1149.1 compatible) 208 qfp package 3.3v or 2.5v core supply with 3.3v i/o supply ? 3.3v core supply is 5v i/o tolerant ejtag in-circuit emulator interface cpu execution core the rc32333 integrates the riscore 32300, the same cpu core found in the award-winning rc32364 microprocessor. the riscore 32300 implements the enhanced mips-ii isa. thus, it is upwardly compatible with applications written for a wide variety of mips architec- ture processors, and it is kernel compatible with the modern operating systems that support idt?s 64-bit riscontroller product family. the riscore 32300 was explicitly defined and designed for integrated processor products such as the rc 32333. key attributes of the execu- tion core found within this product include: high-speed, 5-stage scalar pipeli ne executes to 150mhz. this high performance enables the rc32333 to perform a variety of performance intensive tasks, such as routing, dsp algorithms, etc. 32-bit architecture with enhancements of key capabilities. thus, the rc32333 can execute existing 32-bit programs, while enabling designers to take advantage of recent advances in cpu architecture. count leading-zeroes/ones. these instructions are common to a wide variety of tasks, including modem emulation, voice over ip compression and decompression, etc. cache prefetch instruction support, including a specialized form intended to help memory coherency. system programmers can allocate and stage the use of memory bandwidth to achieve maximum performance. 8kb of 2-way set associative instruction cache figure 2 rc32333 based system diagram sdram flash local i/o serial eeprom serial channel programmable i/o rc32333 32-bit, 50mhz pci local memory i/o bus
3 of 30 may 4, 2004 idt 79rc32333 2kb of 2-way set associative data cache, capable of write-back and write-through operation. cache locking per line to speed r eal-time systems and critical system functions on-chip tlb to enable multi-tasking in modern operating systems ejtag interface to enable sophisticated low-cost in-circuit emulation. synchronous-dram interface the rc32333 integrates a sdram c ontroller which provides direct control of system syncdram running at speeds to 75mhz. key capabilities of the sdram controller include: direct control of 4 banks of sdram (up to 2 64-bit wide dimms) on-chip page comparators opt imize access latency. speeds to 75mhz programmable address map. supports 16, 64, 128, 256, or 512mb sdram devices automatic refresh generation driven by on-chip timer support for discrete devices, sodimm, or dimm modules. thus, systems can take advantage of the full range of commodity memory that is available, enabling system optimization for cost, real- estate, or other attributes. local memory and i/o controller the local memory and i/o contro ller implements direct control of external memory devices, including the boot rom as well as other memory areas, and also implements di rect control of external periph- erals. the local memory controller is highly flexible, allowing a wide range of devices to be directly cont rolled by the rc32333 processor. for example, a system can be built us ing an 8-bit boot rom, 16-bit flash cards (possibly on pcmcia), a 32-bi t sram or dual-port memory, and a variety of low-cost peripherals. key capabilities include: direct control of eprom, flash, ram, and dual-port memories 6 chip-select outputs, supporting up to 8mb per memory space supports mixture of 8-, 16-, and 32-bit wide memory regions flexible timing protocols allow dire ct control of a wide variety of devices programmable address map for 2 chip selects automatic wait state generation. pci bus bridge in order to leverage the wide avail ability of low-co st peripherals for the pc market as well as to simplif y the design of add-in functions, the rc32333 integrates a full 32-bit pci bus bridge. key attributes of this bridge include: 50 mhz operation pci revision 2.2 compliant programmable address mappings between cpu/local memory and pci memory and i/o on-chip pci arbiter extensive buffering allows pci to operate concurrently with local memory transfers selectable byte-ordering swapper. on-chip dma controller to minimize cpu exception handli ng and maximize the efficiency of system bandwidth, the rc32333 integr ates a very sophisticated 4-channel dma controller on chip. the rc32333 dma controller is capable of: chaining and scatter/gather support through the use of a flexible, linked list of dma transaction descriptors capable of memory<->memory, memory<->i/o, and pci<->memory dma unaligned transfer support byte, halfword, word, quadword dma support. on-chip peripherals the rc32333 also integrates peripher als that are common to a wide variety of embedded systems. single 16550 compatible uart. spi master mode interface for direct interface to eeprom, a/d, etc. interrupt controller to speed interrupt decode and management four 32-bit on-chip timer/counters programmable i/o module debug support to facilitate rapid time to ma rket, the rc32333 provides extensive support for system debug. first and foremost, this product integrates an ejtag in-circuit emulation module, allowing a low-co st emulator to interoperate with programs executing on the contro ller. by using an augmented jtag interface, the rc32333 is able to reuse the same low-cost emulators developed around the rc32364 cpu.
4 of 30 may 4, 2004 idt 79rc32333 secondly, the rc32333 implement s additional reporting signals intended to simplify the task of system debugging when using a logic analyzer. this product allows the logi c analyzer to differentiate transac- tions initiated by dma from those initiated by the cpu and further allows cpu transactions to be sorted into instruction fetches vs. data fetches. finally, the rc32333 implements a full boundary scan capability, allowing board manufacturing diagnostics and debug. packaging the rc32333 is packaged using a 208 quad flat pack (qfp) package. thermal considerations the rc32333 consumes less than 2.0 w peak power. the device is guaranteed in an ambient temperature range of 0 to +70 c for commercial temperature devices; -40 to +85 c for industrial tempera- ture devices. revision history march 5, 2003 : initial publication of 2.5v revision x silicon. september 2, 2003 : added 2.5v version of device. changed tables to include 2.5v values where appropriate. added a power consumption table, temperature and voltage table, and power curves for the 2.5v device. in the pci category of tabl e 6, created separate sections for 3.3v and 2.5v devices and in 2.5v section changed time to 4 ns for pci_cbe_n[3:0], pci_frame_n, pci_trdy_n, and pci_irdy_n. in table 8, added 3 new categories (input pads, pci input pads, and all pads) and added footnotes 2 and 3. in table 13, pins 181 and 184 were changed from vcc core to vcc i/o. march 24, 2004 : in table 1, changed description in satellite mode for pci_rst_n. specified ?cold? reset on pages 12 and 13. changed several values in table 12, absolute maximum ratings, and changed footnote 1 to that table. may 4, 2004 : revised values in table 11, power consumption ? 2.5v device.
5 of 30 may 4, 2004 idt 79rc32333 pin description table the following table lists the pins provided on the rc32333. note that those pin names followed by ?_n? are active-low signals. all external pull-ups and pull-downs require 10 k ? resistor. name type reset state status drive strength capability description local system interface mem_data[31:0] i/o z high local system data bus primary data bus for memory. i/o and sdram. mem_addr[22:2] i/o [22:10] z [9:2] l [22:17] low [16:2] high memory address bus these signals provide the memory or dram address, during a memory or dram bus transaction. during each word data, the address increments either in linear or sub-block ordering, depending on the transac- tion type. the table below indicates how the memory write enable signals are used to address discreet memory port width types. mem_addr[22] alternate function: reset_boot_mode[1]. mem_addr[21] alternate function: reset_boot_mode[0]. mem_addr[20] alternate function: reset_pci_host_mode. mem_addr[19] alternate function: modebit [9]. mem_addr[18] alternate function: modebit [8]. mem_addr[17] alternate function: modebit [7]. mem_addr[16] alternate function: sdram_addr[16]. mem_addr[15] alternate function: sdram_addr[15]. mem_addr[14] alternate function: sdram_addr[14]. mem_addr[13] alternate function: sdram_addr[13]. mem_addr[11] alternate function: sdram_addr[11]. mem_addr[10] alternate function: sdram_addr[10]. mem_addr[9] alternate function: sdram_addr[9]. mem_addr[8] alternate function: sdram_addr[8]. mem_addr[7] alternate function: sdram_addr[7]. mem_addr[6] alternate function: sdram_addr[6]. mem_addr[5] alternate function: sdram_addr[5]. mem_addr[4] alternate function: sdram_addr[4]. mem_addr[3] alternate function: sdram_addr[3]. mem_addr[2] alternate function: sdram_addr[2]. mem_cs_n[5:0] output h low memory chip select negated recommend an external pull-up. signals that a memory bank is actively selected. mem_oe_n output h high memory output enable negated recommend an external pull-up. signals that a memory bank can output its data lines onto the cpu_ad bus. mem_we_n[3:0] output h high memory write enable negated bus signals which bytes are to be written during a memory transaction. bits act as byte enable and mem_addr[1:0] signals for 8-bit or 16-bit wide addressing. table 1 pin descriptions (part 1 of 6) port width pin signals mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] dma (32-bit) mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 32-bit mem_we_n[3] mem_we_n[2] mem_we_n[1] mem_we_n[0] 16-bit byte high write enable mem_addr[1] not used (driven low) byte low write enable 8-bit not used (driven high) mem_addr[1] mem_addr[0] byte write enable
6 of 30 may 4, 2004 idt 79rc32333 mem_wait_n input ? memory wait negated requires an external pull-up. sram/ioi/iom modes: allows external wait-states to be injected during the last cycle before data is sam- pled. dpm (dual-port) mode: allows dual-port busy signal to restart memory transaction. alternate function: sdram_wait_n. mem_245_oe_n output h low memory fct245 output enable negated controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to a memory or i/o bank. mem_245_dt_r_n output z high memory fct245 direction xmit/rcv negated recommend an external pull-up. alternate function: cpu_dt_r_n. see cpu core specific signals below. output_clk output cpu_mas terclk high output clock optional clock output. pci interface pci_ad[31:0] i/o z pci pci multiplexed address/data bus address driven by bus master during initial frame_n assertion, and then the data is driven by the bus master during writes; or the data is driven by the bus slave during reads. pci_cbe_n[3:0] i/o z pci pci multiplexed command/byte enable bus command (not negated) bus driven by the bus master during the initial frame_n assertion. byte enable negated bus driven by the bus master during the data phase(s). pci_par i/o z pci pci parity even parity of the pci_ad[31:0] bus. driven by bus master during address and write data phases. driven by the bus slave during the read data phase. pci_frame_n i/o z pci pci frame negated driven by the bus master. assertion indicates the beginning of a bus transaction. de-assertion indicates the last datum. pci_trdy_n i/o z pci pci target ready negated driven by the bus slave to indicate the current datum can complete. pci_irdy_n i/o z pci pci initiator ready negated driven by the bus master to indicate that the current datum can complete. pci_stop_n i/o z pci pci stop negated driven by the bus slave to terminate the current bus transaction. pci_idsel_n input ? pci initialization device select uses pci_req_n[2] pin. see the pci subsection. pci_perr_n i/o z pci pci parity error negated driven by the receiving bus agent 2 clocks after the data is received, if a parity error occurs. pci_serr_n i/o open- collec- tor zpci system error requires an external pull-up. driven by any agent to indicate an address parity error, data parity during a special cycle command, or any other system error. pci_clk input ? pci clock clock for pci bus transactions. uses the rising edge for all timing references. pci_rst_n input l ? pci reset negated host mode: resets all pci related logic. satellite mode: resets all pci related logic and also warm resets the 32333. pci_devsel_n i/o z pci pci device select negated driven by the target to indicate that the target has decoded the present address as a target address. name type reset state status drive strength capability description table 1 pin descriptions (part 2 of 6)
7 of 30 may 4, 2004 idt 79rc32333 pci_req_n[2] input z ? pci bus request #2 negated requires an external pull-up. host mode: pci_req_n[2] is an input indicating a request from an external device. satellite mode: used as pci_idsel pin which selects this device during a configuration read or write. alternate function: pci_idsel (satellite). pci_req_n[1] input z ? pci bus request #1 negated requires external pull-up. host mode: pci_req_n[1] is an input indicating a request from an external device. alternate function: unused (satellite). pci_req_n[0] i/o z high pci bus request #0 negated requires an external pull-up for burst mode. host mode: pci_req_n[0] is an input indicating a request from an external device. satellite mode: pci_req_n[0] is an output indicating a request from this device. pci_gnt_n[2] output z 1 high pci bus grant #2 negated recommend an external pull-up. host mode: pci_gnt_n[2] is an output indicating a grant to an external device. satellite mode: pci_gnt_n[2] is used as the pci_inta_n output pin. external pull-up is required. alternate function: pci_inta_n (satellite). pci_gnt_n[1] / pci_eeprom_cs i/o x for 1 pci clock then h 2 high pci bus grant #1 negated recommend external pull-up. host mode: pci_gnt_n[1] is an output indicating a grant to an external device. satellite mode: used as pci_eprom_cs output pin for serial chip select for loading pci configuration registers in the rc32333 reset initialization vector pci boot mode. defaults to the output direction at reset time. 1st alternate function: pci_eeprom_cs (satellite). 2nd alternate function: pio[7]. pci_gnt_n[0] i/o z high pci bus grant #0 negated host mode: pci_gnt_n[0] is an output indicating a grant to an external device. recommend external pull- up. satellite mode: pci_gnt_n[0] is an input indicating a grant to this device. requires external pull-up. pci_inta_n output open- collec- tor zpci pci interrupt #a negated uses pci_gnt_n[2]. see the pci subsection. pci_lock_n input ? pci lock negated driven by the bus master to indicate that an exclusive operation is occurring. 1 z in host mode; l in satellite non-boot mode; z in satellite boot mode. 2 h in host mode, l in satellite non-boot and boot modes. x = unknown. sdram control interface sdram_addr_12 output l high sdram address bit 12 and precharge all sdram mode: provides sdram address bit 12 (10 on the sdram chip) during row address and "pre- charge all" signal during refresh, read and write command. sdram_ras_n output h high sdram ras negated sdram mode: provides sdram ras control signal to all sdram banks. sdram_cas_n output h high sdram cas negated sdram mode: provides sdram cas control signal to all sdram banks. sdram_we_n output h high sdram we negated sdram mode: provides sdram we control signal to all sdram banks. sdram_cke output h high sdram clock enable sdram mode: provides clock enable to all sdram banks. name type reset state status drive strength capability description table 1 pin descriptions (part 3 of 6)
8 of 30 may 4, 2004 idt 79rc32333 sdram_cs_n[3:0] output h high sdram chip select negated bus recommend an external pull-up. sdram mode: provides chip select to each sdram bank. sodimm mode: provides upper select byte enables [7:4]. sdram_s_n[1:0] output h high sdram sodimm select negated bus sdram mode: not used. sdram sodimm mode: upper and lower chip selects. sdram_bemask_n [3:0] output h high sdram byte enable mask negated bus (dqm) sdram mode: provides byte enables for each byte lane of all dram banks. sodimm mode: provides lower select byte enables [3:0]. sdram_245_oe_n output h low sdram fct245 output enable negated recommend an external pull-up. sdram mode: controls output enable to optional fct245 transceiver bank by asserting during both reads and writes to any dram bank. sdram_245_dt_r_n output z high sdram fct245 direction transmit/receive recommend an external pull-up. uses cpu_dt_r_n. see cpu core specific signals below. on-chip peripherals dma_ready_n[0] i/o z low dma ready negated bus requires an external pull-up. ready mode: input pin for general purpose dma channel 0 that can initiate the next datum in the current dma descriptor frame. done mode: input pin for general purpose dma channel 0 that can terminate the current dma descriptor frame. dma_ready_n[0] 1st alternate function pio[0]; 2nd alternate function: dma_done_n[0]. pio[7:0] i/o see related pins low programmable input/output general purpose pins that can each can be configured as a general purpose input or general purpose output. these pins are multiplexed with other pin functions: pci_gnt_n[1] (pci_eeprom_cs), spi_mosi, spi_sck, spi_ss_n, spi_miso, uart_rx[0], uart_tx[0], dma_ready_n[0]. note that pci_gnt_n[1], spi_mosi, spi_sck, and spi_ss_n default to outputs at reset time. the others default to inputs. uart_rx[0] i/o z low uart receive data bus uart mode: uart channel receive data. uart_rx[0] alternate function: pio[2]. uart_tx[0] i/o z low uart transmit data bus recommend an external pull-up. uart mode: uart channel send data. note that this pin defaults to an input at reset time and must be programmed via the pio interface before being used as a uart output. uart_tx[0] alternate function: pio[1]. spi_mosi i/o l low spi data output serial mode: output pin from rc32333 as an input to a serial chip for the serial data input stream. in pci satellite mode, acts as an output pin from rc32333 that connects as an input to a serial chip for the serial data input stream for loading pci configuration registers in the rc32333 reset initialization vector pci boot mode. 1st alternate function: pio[6]. defaults to the output direction at reset time. 2nd alternate function: pci_eeprom_mdo. spi_miso i/o z low spi data input serial mode: input pin to rc32333 from the output of a serial chip for the serial data output stream. in pci satellite mode, acts as an input pin from rc32333 that connects as an output to a serial chip for the serial data output stream for loading pci configuration registers in the rc32333 reset initialization vector pci boot mode. defaults to input direction at reset time. 1st alternate function: pio[3]. 2nd alternate function: pci_eeprom_mdi. name type reset state status drive strength capability description table 1 pin descriptions (part 4 of 6)
9 of 30 may 4, 2004 idt 79rc32333 spi_sck i/o l low spi clock serial mode: output pin for serial clock. in pci satellite mode, acts as an output pin for serial clock for loading pci configuration registers in the rc323333 reset initialization vector pci boot mode. 1st alternate function: pio[5]. defaults to the output direction at reset time. 2nd alternate function: pci_eeprom_sk. spi_ss_n i/o h low spi chip select output pin selecting the serial protocol device as opposed to the pci satellite mode eeprom device. alternate function: pio[4]. defaults to the output direction at reset time. cpu core specific signals cpu_nmi_n input ? cpu non-maskable interrupt requires an external pull-up. this interrupt input is active low to the cpu. cpu_masterclk input ? cpu master system clock provides the basic system clock. cpu_int_n[1:0] input ? cpu interrupt requires an external pull-up. these interrupt inputs are active low to the cpu. cpu_coldreset_n input l ? cpu cold reset this active-low signal is asserted to the rc32333 after v cc becomes valid on the initial power-up. the reset initialization vectors for the rc32333 are latched by cold reset. cpu_dt_r_n output z ? cpu direction transmit/receive this active-low signal controls the dt/r pin of an optional fct245 transceiver bank. it is asserted during read operations. 1st alternate function: mem_245_dt_r_n. 2nd alternate function: sdram_245_dt_r_n. jtag interface signals jtag_tck input ? jtag test clock requires an external pull-down. an input test clock used to shift into or out of the boundary-scan register cells. jtag_tck is independent of the system and the processor clock with nominal 50% duty cycle. jtag_tdi, ejtag_dint_n input ? jtag test data in requires an external pull-up. on the rising edge of jtag_tck, serial input data are shifted into either the instruction or data register, depending on the tap controller state. during real mode, this input is used as an interrupt line to stop the debug unit from real time mode and return the debug unit back to run time mode (standard jtag). this pin is also used as the ejtag_dint_n signal in the ejtag mode. jtag_tdo, ejtag_tpc output z high jtag test data out the jtag_tdo is serial data shifted out from instruction or data register on the falling edge of jtag_tck. when no data is shifted out, the jtag_tdo is tri-stated. during real time mode, this signal provides a non- sequential program counter at the processor clock or at a division of processor clock. this pin is also used as the ejtag_tpc signal in the ejtag mode. jtag_tms input ? jtag test mode select requires an external pull-up. the logic signal received at the jtag_tms input is decoded by the tap controller to control test operation. jtag_tms is sampled on the rising edge of the jtag_tck. jtag_trst_n input l ? jtag test reset when neither jtag nor ejtag are being used, jtag_trst_n must be driven low (pulled down) or the jtag_tms/ejtag_tms signals must be pulled up and jtag_clk actively clocked. ejtag_dclk output z ? ejtag test clock processor clock. during real time mode, this signal is used to capture address and data from the ejtag_tpc signal at the processor clock speed or any division of the internal pipeline. name type reset state status drive strength capability description table 1 pin descriptions (part 5 of 6)
10 of 30 may 4, 2004 idt 79rc32333 ejtag_pcst[2:0] i/o z low ejtag pc trace status information 111 (stl) pipe line stall 110 (jmp) branch/jump forms with pc output 101 (brt) branch/jump forms with no pc output 100 (exp) exception generated with an exception ve ctor code output 011 (seq) sequential performance 010 (tst) trace is outputted at pipeline stall time 001 (tsq) trace trigger output at performance time 000 (dbm) run debug mode alternate function: modebit[2:0]. ejtag_tms input ? ejtag test mode select requires an external pull-up. the ejtag_tms is sampled on the rising edge of jtag_tck. debug signals debug_cpu_dma_n i/o z low debug cpu versus dma negated de-assertion high during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transac- tion was generated from the cpu. assertion low during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction was generated from dma. alternate function: modebit[6]. debug_cpu_ack_n i/o z low debug cpu acknowledge negated indicates either a data acknowledge to the cpu or dma. alternate function: modebit[4]. debug_cpu_ads_n i/o z low debug cpu address/data strobe negated assertion indicates that either a cpu or a dma transaction is beginning and that the mem_data[31:4] bus has the current block address. alternate function: modebit[5]. debug_cpu_i_d_n i/o z low debug cpu instruction versus data negated assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu or dma data transaction. de-assertion during debug_cpu_ads_n assertion or debug_cpu_ack_n assertion indicates transaction is a cpu instruction transaction. alternate function: modebit[3]. name type reset state status drive strength capability description table 1 pin descriptions (part 6 of 6)
11 of 30 may 4, 2004 idt 79rc32333 logic diagram ? rc32333 rc32333 logic symbol mem_cs_n[5:0] mem_oe_n mem_we_n[3:0] jtag_tck jtag_tms jtag_tdi v cc to i/o gnd mem_wait_n mem_245_oe_n jtag_tdo jtag_trst_n cpu_masterclk cpu_coldreset_n cpu core signals v cc i/o v ss local system jtag power / ground cpu_int_n[1:0] cpu_dt_r_n mem_245_dt_r_n spi_mosi spi_miso spi_ss_n spi_sck sdram_addr[12] sdram_ras_n sdram_cas_n sdram_we_n output_clk uart_rx[0] uart_tx[0] debug_cpu_ack_n debug pci_ad[31:0] pci_cbe_n[3:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[2:0] pci_gnt_n[2:0] interface pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_cs pci_eeprom_mdo pci_eeprom_sk dma_ready_n[0] pio[7:0] pci interface interface mem_addr[22:2] sdram_cke sdram_cs_n[3:0] sdram_bemask_n[3:0] sdram_s_n_[1:0] sdram_245_oe_n dma interface pio uart interface v cc to core v cc core sdram_245_dt_r_n mem_data[31:0] cpu_nmi_n debug_cpu_dma_n debug_cpu_ads_n spi interface sdram signals ejtag_tms ejtag_dclk ejtag_pcst[2:0] ejtag debug_cpu_i_d_n sdram_addr[16:13] sdram_addr[11:2] ejtag_tpc v cc p v ss p
12 of 30 may 4, 2004 idt 79rc32333 mode bit settings to config ure controller on reset the following table lists the mode bit settings to configure the controller on cold reset. reset_boot_mode settings by using the non-boot mode cold reset initialization mode the us er can change the internal regi ster addresses from base 1800_00 00 to base 1900_0000, as required. the rc32333 cold reset-boot mode initiali zation setting values and mode descriptions are listed below. pin mode bit description value mode setting ejtag_pcst[2:0] 2:0 msb (2) clock multiplier masterclock is multiplied internally to gener- ate pclock 0 multiply by 2 1 multiply by 3 2 multiply by 4 3reserved 4reserved 5reserved 6reserved 7reserved debug_cpu_i_d_n 3 endbit 0 little-endian ordering 1 big-endian ordering debug_cpu_ack_n 4 reserved 0 debug_cpu_ads_n 5 reserved 0 debug_cpu_dma_n 6 tmrinten enables/disables the timer interrupt on int*[5] 0 enables timer interrupt 1 disables timer interrupt mem_addr[17] 7 reserved for future use 1 mem_addr[19:18] 9:8 msb (9) boot-prom width specifies the memory port width of the memory space which contains the boot prom. 00 8 bits 01 16 bits 10 32 bits 11 reserved table 2 boot-mode configuration settings pin reset boot mode description value mode settings mem_addr[22:21] 1 :0 msb (1) tri-state memory bus and eeprom bus during coldreset _n assertion 11 tri -state_bus_mode reserved 10 pci-boot mode (pci_host_mode must be in satellite mode) rc32333 will reset either from a cold reset or from a pc i reset. boot code is provided via pci. 01 pci_boot_mode standard-boot mode boot from the rc32333?s memory controller (typical system). 00 standard_boot_mode table 3 rc32333 reset_boot_mode initialization settings
13 of 30 may 4, 2004 idt 79rc32333 pci_host_mode settings during cold reset initialization, the rc32333?s pci interface c an be set to the satellite or host mode settings. when set to th e host mode, the cpu must configure the rc32333?s pci c onfiguration registers, includi ng the read-only registers. if the rc32333?s pci is in the pci -boot mode satellite mode, read-only configuration register s are loaded by the serial eeprom. clock parameters ? rc32333 ta commercial = 0 c to +70 c; ta industrial = -40 c to +85 c 3.3v version : v cc core = +3.3v 5%; v cc i/o = +3.3v 5% 2.5v version : v cc core = +2.5v 5%; v cc i/o = +3.3v 5% pin reset boot mode description value mode settings mem_addr[20] pci host mode pci is in satellite mode 1 pci_satellite pci is in host mode (typical system) 0 pci_host table 4 rc32333 pci_host_mode initialization settings parameter symbol test conditions rc32333 100mhz rc32333 133mhz rc32333 150mhz units min max min max min max cpu_masterclock high t mchigh transition 2ns 8 ? 6.75 ? 6 ? ns cpu_masterclock low t mclow transition 2ns 8 ? 6.75 ? 6 ? ns cpu_masterclock period 1 - 3.3v ver. 1. cpu_masterclock frequency should never be below pci_clk frequency if pci interface is used. t mcp ? 20 66.6 15 66.6 13.33 66.6 ns cpu_masterclock period 1 - 2.5v ver. t mcp ? 20 40.0 15 40.0 13.33 40.0 ns cpu_masterclock rise & fall time 2 2. rise and fall times are measured between 10% and 90%. t mcrise, t mcfall ? ?3?3?3ns cpu_masterclock jitter t jitter ??+ 250 ? + 250 ? + 200 ps pci_clk rise & fall time t pcrise, t pcfall pci 2.2 ? 1.6 ? 1.6 ? 1.6 ns pci_clk period 1 t pcp 20 ? 20 ? 20 ? ns jtag_tck rise & fall time t jcrise, t jcfall ? ?5?5?5ns ejtag_dck period t dck, t 11 10 ? 10 ? 10 ? ns jtag_tck clock period t tck, t 3 100?100?100? ns ejtag_dclk high, low time t dck high, t 9 t dck low, t 10 4?4?4?ns ejtag_dclk rise, fall time t dck rise, t 9 t dck fall, t 10 ?1?1?1ns output_clk 3 3. output_clk should not be used in a system. only the cpu_mastercl ock or its derivative must be used to drive all the subsystems with designs based on the rc3233x systems. refer to the rc3233x device errata for more information. t do 21 n/a n/a n/a n/a n/a n/a ? cpu_coldreset_n asserted during power-up power-on sequence 120 ? 120 ? 120 ? ms cpu_coldreset_n rise time t crrise ?5?5?5ns table 5 clock parameters - rc32333
14 of 30 may 4, 2004 idt 79rc32333 reset specification figure 3 mode configuration interface cold reset sequence vcc cpu_coldreset_n modebit[9:0] >= 110 ms cpu_masterclk >= 10 ms (mclk) 120 ms t crrise
15 of 30 may 4, 2004 idt 79rc32333 ac timing characteristics ? rc32333 ta commercial = 0 c to +70 c; ta industrial = -40 c to +85 c 3.3v version : v cc core = +3.3v 5%; v cc i/o = +3.3v 5% 2.5v version : v cc core = +2.5v 5%; v cc i/o = +3.3v 5% signal symbol reference edge rc32333 1 100mhz rc32333 1 133mhz rc32333 1 150mhz units user manual timing diagram reference min max min max min max local system interface mem_data[31:0] (data phase) tsu2 cpu_masterclk rising 6 ? 5 ? 4.8 ? ns chapter 9, figures 9.2 and 9.3 chapter 10, figures 10.6 through 10.8 mem_data[31:0] (data phase) thld2 cpu_masterclk rising 1.5 ? 1.5 ? 1.5 ? ns cpu_dt_r_n tdo3 cpu_masterclk rising ? 15 ? 12 ? 10 ns mem_data[31:0] tdo4 cpu_masterclk rising ? 12 ? 10 ? 9.3 ns mem_data[31:0] output hold time tdoh1 cpu_masterclk rising 1 ? 1 ? 1 ? ns mem_data[31:0] (tristate disable time) tdz cpu_masterclk rising ? 12 2 ?10 2 ?9.3 2 ns mem_data[31:0] (tristate to data time) tzd cpu_masterclk rising ? 12 2 ?10 2 ?9.3 2 ns mem_wait_n tsu6 cpu_masterclk rising 9 ? 7 ? 6 ? ns mem_wait_n thld8 cpu_masterclk rising 1 ? 1 ? 1 ? ns mem_addr[22:2] tdo5 cpu_masterclk rising ? 12 ? 9 ? 8 ns mem_cs_n[5:0] tdo6 cpu_masterclk rising ? 12 ? 9 ? 8 ns mem_oe_n, mem_245_oe_n tdo7 cpu_masterclk rising ? 12 ? 9 ? 8 ns mem_we_n[3:0] tdo7a cpu_masterclk rising ? 15 ? 12 ? 10 ns mem_245_dt_r_n tdo8 cpu_masterclk rising ? 15 ? 12 ? 10 ns mem_addr[25:2] mem_cs_n[5:0] mem_oe_n, mem_we_n[3:0], mem_245_dt_r_n, mem_245_oe_n tdoh3 cpu_masterclk rising 1.5 ? 1.5 ? 1.5 ? ns pci for 3.3v device 3 pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n tsu pci_clk rising 3?3?3?ns pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n tsu pci_clk rising 5?5?5?ns pci_gnt_n[0] tsu pci_clk rising 5 ? 5 ? 5 ? ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n 4 thld pci_clk rising 0?0?0?ns table 6 ac timing characteristics - rc32333 (part 1 of 4)
16 of 30 may 4, 2004 idt 79rc32333 pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n thld pci_clk rising 0?0?0?ns pci_eeprom_mdi tsu pci_clk rising, pci_eeprom_sk falling 15 ? 12 ? 10 ? ns pci_eeprom_mdi thld pci_clk rising, pci_eeprom_sk falling 15 ? 12 ? 10 ? ns pci_eeprom_mdo, pci-eeprom_cs tdo pci_clk rising, pci_eeprom_sk falling ?15?12?10 ns pci_eeprom_sk tdo pci_clk rising ? 15 ? 12 ? 10 ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n tdo pci_clk rising 27.527.527.5ns pci_req_n[0], pci_gnt_[2], pci_gnt_n[1], pci_gnt_n[0], pci_inta_n tdo pci_clk rising 27.527.527.5ns pci for 2.5v device 3 pci_ad[31:0], pci_par, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n 4 tsu pci_clk rising 3?3?3?ns pci_cbe_n[3:0], pci_frame_n, pci_trdy_n, pci_irdy_n tsu pci_clk rising 4?4?4?ns pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n tsu pci_clk rising 5?5?5?ns pci_gnt_n[0] tsu pci_clk rising 5 ? 5 ? 5 ? ns pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n, pci_lock_n 4 thld pci_clk rising 0?0?0?ns pci_idsel, pci_req_n[2], pci_req_n[1], pci_req_n[0], pci_gnt_n[0], pci_inta_n thld pci_clk rising 0?0?0?ns pci_eeprom_mdi tsu pci_clk rising, pci_eeprom_sk falling 15 ? 12 ? 10 ? ns pci_eeprom_mdi thld pci_clk rising, pci_eeprom_sk falling 15 ? 12 ? 10 ? ns pci_eeprom_mdo, pci-eeprom_cs tdo pci_clk rising, pci_eeprom_sk falling ?15?12?10 ns pci_eeprom_sk tdo pci_clk rising ? 15 ? 12 ? 10 ns signal symbol reference edge rc32333 1 100mhz rc32333 1 133mhz rc32333 1 150mhz units user manual timing diagram reference min max min max min max table 6 ac timing characteristics - rc32333 (part 2 of 4)
17 of 30 may 4, 2004 idt 79rc32333 pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n tdo pci_clk rising 27.527.527.5ns pci_req_n[0], pci_gnt_[2], pci_gnt_n[1], pci_gnt_n[0], pci_inta_n tdo pci_clk rising 27.527.527.5ns sdram controller sdram_245_dt_r_n tdo8 cpu_masterclk rising ? 15 ? 12 ? 10 ns chapter 11, figures 11.4 and 11.5 sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0], sdram_cke tdo9 cpu_masterclk rising ? 12 ? 9 ? 8 ns sdram_addr_12 tdo10 cpu_masterclk rising ? 12 ? 9 ? 8 ns sdram_245_oe_n tdo11 cpu_masterclk rising ? 12 ? 9 ? 8 ns sdram_245_dt_r_n tdoh4 cpu_masterclk rising 1 ? 1 ? 1 ? ns sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0] sdram_cke, sdram_addr_12, sdram_245_oe_n tdoh4 cpu_masterclk rising 2.5 ? 2.5 ? 2.5 ? ns dma dma_ready_n[0], dma_done_n[0] tsu7 cpu_masterclk rising 9 ? 7 ? 6 ? ns chapter 13, figure 13.4 dma_ready_n[0], dma_done_n[0] thld9 cpu_masterclk rising 1 ? 1 ? 1 ? ns interrupt handling cpu_int_n[1:0], cpu_nmi_n tsu9 cpu_masterclk rising 9 ? 7 ? 6 ? ns chapter 14, figure 14.12 cpu_int_n[1:0], cpu_nmi_n thld13 cpu_masterclk rising 1 ? 1 ? 1 ? ns pio pio[7:0] tsu7 cpu_masterclk rising 9 ? 7 ? 6 ? ns chapter 15, figures 15.9 and 15.10 pio[7:0] thld9 cpu_masterclk rising 1 ? 1 ? 1 ? ns pio[7:6], pio[4:0] tdo16 cpu_masterclk rising ? 15 ? 12 ? 10 ns pio[5] tdo19 cpu_masterclk rising ? 15 ? 12 ? 10 ns pio[7:6], pio[4:0] tdoh7 cpu_masterclk rising 1 ? 1 ? 1 ? ns pio[5] tdoh7 cpu_masterclk rising 1 ? 1 ? 1 ? ns uarts uart_rx[0], uart_tx[0] tsu7 cpu_masterclk rising 15 ? 12 ? 10 ? ns chapter 17, figure 17.16 uart_rx[0], uart_tx[0] thld9 cpu_masterclk rising 15 ? 12 ? 10 ? ns uart_rx[0], uart_tx[0] tdo16 cpu_masterclk rising ? 15 ? 12 ? 10 ns uart_rx[0], uart_tx[0] tdoh8 cpu_masterclk rising 1 ? 1 ? 1 ? ns signal symbol reference edge rc32333 1 100mhz rc32333 1 133mhz rc32333 1 150mhz units user manual timing diagram reference min max min max min max table 6 ac timing characteristics - rc32333 (part 3 of 4)
18 of 30 may 4, 2004 idt 79rc32333 reset mem_addr[19:17] tsu10 cpu_coldreset_n rising 10 ? 10 ? 10 ? ms chapter 19, figures 19.8 and 19.9 mem_addr[19:17] thld10 cpu_coldreset_n rising 1 ? 1 ? 1 ? ns mem_addr[22:20] tsu22 cpu_masterclk rising 9 ? 7 ? 6 ? ns mem_addr[22:20] thld22 cpu_masterclk rising 1 ? 1 ? 1 ? ns debug interface debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] tsu20 cpu_coldreset_n rising 10 ? 10 ? 10 ? ms debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n, ejtag_pcst[2:0] thld20 cpu_coldreset_n rising 1 ? 1 ? 1 ? ns chapter 19, figure 19.9 and chapter 9, figure 9.2 debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n tdo20 cpu_masterclk rising ? 15 ? 12 ? 10 ns debug_cpu_dma_n, debug_cpu_ack_n, debug_cpu_ads_n, debug_cpu_i_d_n tdoh20 cpu_masterclk rising 1 ? 1 ? 1 ? ns jtag interface jtag_tms, jtag_tdi, jtag_trst_n t 5 jtag_tck rising 10 ? 10 ? 10 ? ns see figure 4 below. jtag_tms, jtag_tdi, jtag_trst_n t 6 jtag_tck rising 10 ? 10 ? 10 ? ns jtag_tdo t 4 jtag_tck falling ? 10 ? 10 ? 10 ns ejtag interface ejtag_tms t 5 jtag_tclk rising 4?4?4?ns ejtag_tms t 6 jtag_clk rising 2 ? 2 ? 2 ? ns jtag_tdo output delay time t tdodo, t 4 jtag_tck falling ? 6 ? 6 ? 6 ns see figure 4 below. jtag_tdi input setup time t tdis, t 5 jtag_tck rising 4 ? 4 ? 4 ? ns jtag_tdi input hold time t tdih, t 6 jtag_tck rising 2 ? 2 ? 2 ? ns jtag_trst_n low time t trstlow, t 12 ? 100 ? 100 ? 100 ? ns jtag_trst_n removal time t trstr, t 13 jtag_tck rising 3 ? 3 ? 3 ? ns ejtag_tpc output delay time t tpcdo, t 8 ejtag_dclk rising -13-13-13 ns ejtag_pcst output delay time t pcstdo, t 7 ejtag_dclk rising -13-13-13 ns 1. at all pipeline frequencies. 2. guaranteed by design. 3. this pci interface conforms to the pci local bus specification, rev 2.2 at 33mhz. 4. pci_rst_n is tested per pci 2.2 as an asynchronous signal. signal symbol reference edge rc32333 1 100mhz rc32333 1 133mhz rc32333 1 150mhz units user manual timing diagram reference min max min max min max table 6 ac timing characteristics - rc32333 (part 4 of 4)
19 of 30 may 4, 2004 idt 79rc32333 standard ejtag timing ? rc32333 figure 4 represents the timing diagram for the ejtag interface signals. the standard jtag connector is a 10-pin c onnector providing 5 signals and 5 ground pins . for standard ejtag, a 24-pin connector has been chosen providing 12 signals and 12 ground pins. this guarantees elimination of noi se problems by incor porating signal-ground ty pe arrangement. refer to the rc3233x user reference manual for connector pinout and mechanical specifications. figure 4 standard ejtag timing jtag_tdi/ejtag_dint_n ejtag_tms, jtag_tms jtag_tdo/ejtag_tpc, ejtag_tpc[8:2] jtag_tdo jtag_tdo ejtag_tpc ejtag_pcst[2:0] jtag_trst_n jtag_tck ejtag_dclk ejtag_pcst t3 t14 t14 t1 t2 t15 t15 t9 t10 t5 t6 t4 t8 t7 t13 t12 t11 ejtag_tpc,ejtag_pcst[2:0] capture notes to diagram: t1 = t tcklow t2 = t tckhigh t3 = t tck t4 = t tdodo t5 = t tdis t6 = t tdih t7 = t pcstdo t8 = t tpcdo t9 = t dckhigh t10 = t dcklow t11 = t dck t12 = t trstdo t13 = t trstr t14 = t tck rise, ttck fall t15 = t dck rise, t dck fall
20 of 30 may 4, 2004 idt 79rc32333 output loading for ac testing note: pci pins have been correlated to pci 2.2. recommended operation temper ature and supply voltage 3.3v device 2.5v device signal cld all high drive signals 50 pf all low drive signals 25 pf figure 5 output loading for ac testing grade ambient temperature gnd v cc io v cc core v cc p commercial 0 c to +70 c ambient 0v 3.3v5% 3.3v5% 3.3v5% industrial -40 c to +85 c ambient 0v 3.3v5% 3.3v5% 3.3v5% table 7 temperature and voltage ? 3.3v device grade ambient temperature gnd v cc io v cc core v cc p commercial 0 c to +70 c ambient 0v 3.3v5% 2.5v5% 2.5v5% industrial -40 c to +85 c ambient 0v 3.3v5% 2.5v5% 2.5v5% table 8 temperature and voltage ? 2.5v device ? + to device under test c ld v ref +1.5v
21 of 30 may 4, 2004 idt 79rc32333 dc electrical charac teristics ? rc32333 ta commercial = 0 c to +70 c; ta industrial = -40 c to +85 c 3.3v version : v cc core = +3.3v 5%; v cc i/o = +3.3v 5% 2.5v version : v cc core = +2.5v 5%; v cc i/o = +3.3v 5% capacitive load deration ? rc32333 refer to the idt document 7 9rc32333 ibis model which can be found on the company?s web site at www.idt.com. parameter rc32333 1 1. at all pipeline frequencies. pin numbers conditions minimum maximum input pads v il ? 0.8v 52, 64, 95, 161, 162, 165, 167-170, 191 ? v ih 2.0v ? ? low drive output- pads v ol ? 0.4v 41-45, 48, 171, 172, 175, 176, 177-180, 185-190, 195-200, 207, 208 |i out | = 6ma v oh v cc - 0.4v ? |i out | = 8ma v il ?0.8v ? v ih 2.0v ? ? high drive out- put pads v ol ? 0.4v 1- 5, 8, 13-15, 18-25, 28-35, 38-40, 49-51, 53- 57, 60, 61, 63, 65- 67,70-76, 79, 80, 83-87, 90-94, 153, 154, 156, 159, 166, 194, 201, 204, 205, 206 |i out | = 7ma v oh v cc - 0.4v ? |i out | = 16ma v il ?0.8v ? v ih 2.0v ? ? pci drive input pads v il ? ? 123, 155, 157, 158, 160 per pci 2.2 v ih ?? pci drive output pads v ol ? ? 96, 97, 100-109, 112-119, 122, 124-129, 132-139, 142-149, 152 per pci 2.2 v oh ?? v il ?? v ih ?? all pads c in ? 10pf all input pads except 155 and 156 ? c in 2 2. applies only to pad 155. 5pf 12pf 155 per pci 2.2 c in 3 3. applies only to pad 156. 8pf 156 per pci 2.2 c out ? 10pf all output pads ? i/o leak ?10 a all non-internal pull-up pins input/output leakage i/o leak ?50 a all internal pull-up pins input/output leakage table 9 dc electrical characteristics - rc32333
22 of 30 may 4, 2004 idt 79rc32333 power consumption 3.3v device note: this table is based on a 2:1 pi peline-to-bus clock ratio. 2.5v device note: this table is based on a 2:1 pi peline-to-bus clock ratio. power ramp-up 3.3v device there is no special requi rement for how fast v cc i/o ramps up to 3.3v. however, all timing references are based on a stable v cc i/o. 2.5v device the 2.5v core supply (and 2.5v v cc p supply) can be fully powered without the 3.3v i/o s upply. however, the 3.3v i/o supply cannot exceed the 2.5v core supply by more than 1 volt during power up. a su stained large power difference c ould potentially damage the part. inp uts should not be driven until the part is fully powered. spec ifically, the input high voltages should not be applied until the 3.3v i/o supply i s powered. there is no special requi rement for how fast v cc i/o ramps up to 3.3v. however, all timing references are based on a stable v cc i/o. parameter 100mhz 133mhz 150mhz unit conditions typical max. typical max. typical max. i cc normal mode 360 480 480 630 550 700 ma c l = (see figure 5, output loading for ac testing) t a = 25 o c v cc core = 3.46v (for max. values) v cc i/o = 3.46v (for max. values) v cc core = 3.3v (for typical values) v cc i/o = 3.3v (for typical values) standby mode 1 1. riscore 32300 cpu core enters standby mode by executing wait inst ructions. on-chip logic outside the cpu core continues to func tion. 250 370 330 480 390 540 ma power dissipation normal mode 1.2 1.7 1.5 2.2 1.7 2.4 w standby mode 1 0.83 1.3 1.1 1.7 1.3 1.9 w table 10 power consumption ? 3.3v device parameter 100mhz 133mhz 150mhz unit conditions typical max. typical max. typical max. i cc i/o normal mode 24 81 32 93 35 104 ma c l = (see figure 5, output loading for ac testing) t a = 25 o c v cc core = 2.625v (for max. values) v cc i/o = 3.46v (for max. values) v cc core = 2.5v (for typical values) v cc i/o = 3.3v (for typical values) standby mode 1 1. riscore 32300 cpu core enters standby mode by executing wait inst ructions. on-chip logic outside the cpu core continues to func tion. 2812932104ma i cc core normal mode 232 301 298 392 333 438 ma standby mode 1 120 269 151 319 168 345 ma power dissipation normal mode 0.66 1.07 0.85 1.35 0.95 1.51 w standby mode 1 0.31 0.94 0.38 1.10 0.43 1.21 w table 11 power consumption ? 2.5v device
23 of 30 may 4, 2004 idt 79rc32333 power curves the following four graphs contain the simula ted power curves that show power consum ption at various bus frequencies. figures 6 and 7 apply to the 3.3v device, while figures 8 and 9 apply to the 2.5v device. figure 6 typical power usage ? rc32v333 device . figure 7 maximum power usage ? rc32v333 device 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 50 55 60 65 70 75 system bus speed (mhz) power (w@3.3v i/o & core) 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 50 55 60 65 70 75 system bus speed (mhz) power (w@3.46v i/o & core)
24 of 30 may 4, 2004 idt 79rc32333 figure 8 typical power usage ? rc32t333 device figure 9 maximum power usage ? rc32t333 device 0.65 0.70 0.75 0.80 0.85 0.90 0.95 50 55 60 65 70 75 system bus speed (mhz) power (w@3.3v i/o & 2.5v core) 1.0 1.1 1.2 1.3 1.4 1.5 1.6 50 55 60 65 70 75 system bus speed (mhz) power (w@3.46v i/o & 2.625v core)
25 of 30 may 4, 2004 idt 79rc32333 absolute maximum ratings package pin-out ? 208-pqfp for rc32333 the following table lists the pin number s and signal names for the rc32333. signal nam es ending with an _n are active when low. symbol parameter min 1 1. functional and tested operating conditions are given in t able 7. absolute maximum ratings are stress ratings only, and functional operation is not guaranteed beyond reco mmended operating voltages and temperatures. stresses be- yond those listed may affect device reliability or cause permanent damage to the device. max 1 unit v cc core 3.3v device supply voltage -0.3 4.0 v v cc core 2.5v device supply voltage -0.3 3.0 v v cc i/o i/o supply voltage -0.3 4.0 v vi 3.3v device input voltage -0.3 5.5 v vi 2.5v device input voltage -0.3 v cc i/o+0.3 v vimin input voltage - undershoot 2 2. all pci pads are fully compatible with pci specification version 2.2. -0.6 ? v tstg storage temperature -40 125 degrees c table 12 absolute maximum ratings pin function alt pin function alt pin function alt pin function alt 1 sdram_245_oe_n 53 mem_data[12] 105 pci_ad[7] 157 pci_req_n[1] 2 sdram_we_n 54 mem_data[19] 106 pci_cbe_n[0] 158 pci_req_n[2] 1 3 sdram_cas_n 55 mem_data[13] 107 pci_ad[8] 159 pci_gnt_n[2] 1 4 sdram_bemask_n[0] 56 mem_data[18] 108 pci_ad[9] 160 pci_rst_n 5 sdram_bemask_n[1] 57 mem_data[14] 109 pci_ad[10] 161 cpu_int_n[0] 6v ss 58 v ss 110 v ss 162 cpu_int_n[1] 7v cc i/o 59 v cc i/o 111 v cc i/o 163 v ss 8 sdram_cs_n[0] 60 mem_data[17] 112 pci_ad[11] 164 v cc i/o 9 sdram_cs_n[1] 61 mem_data[16] 113 pci_ad[12] 165 jtag_tdi 10 sdram_ras_n 62 v cc core 114 pci_ad[13] 166 jtag_tdo 11 sdram_s_n[0] 63 mem_data[15] 115 pci_ad[14] 167 jtag_tms 12 sdram_s_n[1] 64 cpu_masterclk 116 pci_ad[15] 168 ejtag_tms 13 mem_addr[2] 1 65 mem_data[31] 117 pci_cbe_n[1] 169 jtag_tck 14 mem_addr[3] 1 66 mem_data[0] 118 pci_par 170 jtag_trst_n 15 mem_addr[4] 1 67 mem_data[30] 119 pci_serr_n 171 ejtag_pcst[0] 1 16 v ss 68 v ss 120 v ss 172 ejtag_pcst[1] 1 17 v cc i/o 69 v cc i/o 121 v cc i/o 173 v ss 18 mem_addr[5] 1 70 mem_data[1] 122 pci_perr_n 174 v cc i/o table 13 rc32333 208-pin qfp package pin-out (part 1 of 2)
26 of 30 may 4, 2004 idt 79rc32333 19 mem_addr[6] 1 71 mem_data[29] 123 pci_lock_n 175 ejtag_pcst[2] 1 20 mem_addr[7] 1 72 mem_data[2] 124 pci_stop_n 176 ejtag_dclk 21 mem_addr[8] 1 73 mem_data[28] 125 pci_devsel_n 177 debug_cpu_i_d_n 1 22 mem_addr[9] 1 74 mem_data[3] 126 pci_trdy_n 178 debug_cpu_ads_n 1 23 mem_addr[10] 1 75 mem_data[27] 127 pci_irdy_n 179 debug_cpu_ack_n 1 24 mem_addr[11] 1 76 mem_data[4] 128 pci_frame_n 180 debug_cpu_dma_n 1 25 output_clk 77 v cc p 129 pci_cbe_n[2] 181 v cc i/o 26 v ss 78 v ss p 130 v ss 182 v ss 27 v cc core 79 mem_data[26] 131 v cc core 183 v cc core 28 mem_addr_12 80 mem_data[5] 132 pci_ad[16] 184 v cc i/o 29 sdram_addr_12 81 v ss 133 pci_ad[17] 185 spi_ss_n 1 30 sdram_cke 82 v cc core 134 pci_ad[18] 186 spi_sck 2 31 sdram_cs_n[2] 83 cpu_dt_r_n 2 135 pci_ad[19] 187 spi_miso 2 32 sdram_cs_n[3] 84 mem_data[25] 136 pci_ad[20] 188 spi_mosi 2 33 sdram_bemask_n[2] 85 mem_data[6] 137 pci_ad[21] 189 dma_ready_n[0] 2 34 sdram_bemask_n[3] 86 mem_data[24] 138 pci_ad[22] 190 mem_245_oe_n 35 mem_addr[13] 87 mem_data[7] 139 pci_ad[23] 191 mem_wait_n 2 36 v ss 88 v ss 140 v ss 192 v ss 37 v cc i/o 89 v cc i/o 141 v cc i/o 193 v cc i/o 38 mem_addr[14] 90 mem_data[23] 142 pci_cbe_n[3] 194 mem_oe_n 39 mem_addr[15] 1 91 mem_data[8] 143 pci_ad[24] 195 mem_cs_n[0] 40 mem_addr[16] 1 92 mem_data[22] 144 pci_ad[25] 196 mem_cs_n[1] 41 mem_addr[17] 1 93 mem_data[9] 145 pci_ad[26] 197 mem_cs_n[2] 42 mem_addr[18] 1 94 mem_data[21] 146 pci_ad[27] 198 mem_cs_n[3] 43 mem_addr[19] 1 95 cpu_nmi_n 147 pci_ad[28] 199 mem_cs_n[4] 44 mem_addr[20] 1 96 pci_ad[0] 148 pci_ad[29] 200 mem_cs_n[5] 45 mem_addr[21] 1 97 pci_ad[1] 149 pci_ad[30] 201 mem_we_n[0] 46 v ss 98 v ss 150 v ss 202 v ss 47 v cc i/o 99 v cc i/o 151 v cc i/o 203 v cc i/o 48 mem_addr[22] 1 100 pci_ad[2] 152 pci_ad[31] 204 mem_we_n[1] 49 mem_data[10] 101 pci_ad[3] 153 pci_req_n[0] 205 mem_we_n[2] 50 mem_data[11] 102 pci_ad[4] 154 pci_gnt_n[0] 206 mem_we_n[3] 51 mem_data[20] 103 pci_ad[5] 155 pci_clk 207 uart_tx[0] 1 52 cpu_coldreset_n 104 pci_ad[6] 156 pci_gnt_n[1] 2 208 uart_rx[0] 1 pin function alt pin function alt pin function alt pin function alt table 13 rc32333 208-pin qfp package pin-out (part 2 of 2)
27 of 30 may 4, 2004 idt 79rc32333 rc32333 alternate signal functions table 14 rc32333 alternate signal functions pin alt #1 alt #2 pin alt #1 alt #2 pin alt #1 alt #2 13 sdram_addr[2] 40 sdram_addr[16] 175 modebit[2] 14 sdram_addr[3] 41 modebit[7] 177 modebit[3] 15 sdram_addr[4] 42 modebit[8] 178 modebit[5] 18 sdram_addr[5] 43 modebit[9] 179 modebit[4] 19 sdram_addr[6] 44 reset_pci_host_mode 180 modebit[6] 20 sdram_addr[7] 45 reset_boot_mode[0] 185 pio[4] 21 sdram_addr[8] 48 reset_boot_mode[1] 186 pio[5] pci_eeprom_sk 22 sdram_addr[9] 83 mem_245_dt_r_n sdram_245_dt_r_n 187 pio[3] pci_eeprom_mdi 23 sdram_addr[10] 156 pci_eeprom_cs (satellite) pio[7] 188 pio[6] pci_eeprom_mdo 24 sdram_addr[11] 158 pci_idsel (satellite) 189 pio[0] dma_done_n[0] 35 sdram_addr[13] 159 pci_inta_n (satellite) 191 sdram_wait_n mem_wait_n 38 sdram_addr[14] 171 modebit[0] 207 pio[1] 39 sdram_addr[15] 172 modebit[1] 208 pio[2]
28 of 30 may 4, 2004 idt 79rc32333 rc32333 package drawing ? 208-pin pqfp
29 of 30 may 4, 2004 idt 79rc32333 rc32333 package drawing ? page two
30 of 30 may 4, 2004 idt 79rc32333 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-330-1748 www.idt.com for tech support: email: rischelp@idt.com phone: 408-492-8208 ordering information valid combinations 3.3v device 2.5v device 79rc32v333 - 100dh, 133dh, 150dh commercial 79rc32v333 - 100dhi, 133dhi, 150dhi industrial 79rc32t333 - 100dh, 133dh, 150dh commercial 79rc32t333 - 100dhi, 133dhi, 150dhi industrial 79rcxx v ddd sss pp operating voltage device type v = 3.3v 5% product type 79rc32 = 32-bit family product cpu frequency 100mhz 133mhz package temp range/ process blank = commercial temperature (0 c to +70 c ambient) i = industrial temperature (-40 c to +85 c ambient) dh = 208-pin pqfp 333 150mhz t = 2.5v 5%

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